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DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Latest commits for file .gitattributes | 2 | 10k | Resistor | | | | | | Tayda | A-1672 | | | D3, D4, D5, D6, D7, D8, D9, D10 100V 0.15A standard switching diode, DO-35 | | | | C7, C11 | 3 | A1M | Potentiometer | | | | U2 | 1 | SW_Push | Push.

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