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BackFolders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: merged pull request synth_mages/MK_VCO#5 Final revision; added custom DRC as project file tstamp 885d8854-95c7-40d1-bee9-0e598504ab1c) Final revision; added custom DRC as project file tstamp a19ef654-a631-44b9-8b6b-999333495c1b) Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file tstamp e90beec6-952b-474b-a043-0f4708c5b9c2) Final revision; added custom DRC as project file tstamp 885d8854-95c7-40d1-bee9-0e598504ab1c) Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file tstamp 62e17d71-a82e-47f7-8a14-a0885fbe0008) Final.
- 0.528347 0.643664 0.553666 facet normal -0.192217.
- 45degree), 16 pins, pitch.
- Normal -0.0824715 0.0562099 0.995007 vertex 7.19917 -3.46694 19.9405.