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README.md

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+Notes:
+
+- Could make the clock oscillilator an external module, with the SEQ listening for a clock on the 16-pin IDC connector when nothing is plugged into CLOCK.
+- A notable issue with this design is the decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock sources cycle between 0v and 5v or even much less.  
+This can be fixed by increasing the gain on the CLOCK op-amp from 1 to something more decisive, like 3x.  Then a signal as low as 2v could works as an external clock.
+- One idea: add a switch to disable the clock, and a momentary-on button to advance the step manually.  This requires hardware de-bouncing to avoid multiple triggers on each 
+button push.
+- Could replace step IDs with a 7-segment display with a diode matrix to select segments from each step.
+
+
+
+UI:
+  11 potentiometers
+  11 SPDT switches
+  1 rotary switch, 5+ positions
+  10 LEDs
+  3 sockets
+
+Potentiometers:
+	One potentiometer per step, to set output voltages. (10)
+	One potentiometer for internal clock rate.
+
+Switches:
+	One SPDT switch per step, to enable/disable gate per step. (10)
+	One multi-pole rotary switch to set number of steps.  Exact configuration TBD.
+        One SPDT switch to adjust CV output range, switch between 5v and 2.5v max.
+	
+LEDs:
+	One per step, to indicate current step.  (10)
+	
+Sockets:
+	CLOCK in
+        CLOCK out
+        RESET in
+	GATE out
+	CV out