Finished PCB, passes all passable DRCs
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2666d5803f
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3 changed files with 55976 additions and 2532 deletions
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@ -34,9 +34,9 @@
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"other_text_thickness": 0.15,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"other_text_upright": false,
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"pads": {
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"pads": {
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"drill": 0.5,
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"drill": 1.0,
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"height": 0.85,
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"height": 1.7,
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"width": 0.85
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"width": 1.7
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},
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},
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"silk_line_width": 0.15,
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"silk_line_width": 0.15,
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"silk_text_italic": false,
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"silk_text_italic": false,
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@ -426,10 +426,27 @@
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"name": "Default",
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"track_width": 0.3,
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"via_diameter": 0.8,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"via_drill": 0.4,
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"wire_width": 6
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Power",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.6,
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"via_diameter": 1.0,
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"via_drill": 0.5,
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"wire_width": 6
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}
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}
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],
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],
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"meta": {
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"meta": {
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@ -437,7 +454,20 @@
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},
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},
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"net_colors": null,
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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"netclass_patterns": [
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{
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"netclass": "Power",
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"pattern": "+12V"
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},
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{
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"netclass": "Power",
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"pattern": "-12V"
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},
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{
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"netclass": "Power",
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"pattern": "GND"
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}
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]
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},
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},
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"pcbnew": {
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"pcbnew": {
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"last_paths": {
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"last_paths": {
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