Finished PCB, passes all passable DRCs

This commit is contained in:
George Dorn 2023-10-23 18:11:51 -07:00
parent 2666d5803f
commit 3583986e89
3 changed files with 55976 additions and 2532 deletions

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@ -34,9 +34,9 @@
"other_text_thickness": 0.15, "other_text_thickness": 0.15,
"other_text_upright": false, "other_text_upright": false,
"pads": { "pads": {
"drill": 0.5, "drill": 1.0,
"height": 0.85, "height": 1.7,
"width": 0.85 "width": 1.7
}, },
"silk_line_width": 0.15, "silk_line_width": 0.15,
"silk_text_italic": false, "silk_text_italic": false,
@ -426,10 +426,27 @@
"name": "Default", "name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25, "track_width": 0.3,
"via_diameter": 0.8, "via_diameter": 0.8,
"via_drill": 0.4, "via_drill": 0.4,
"wire_width": 6 "wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6,
"via_diameter": 1.0,
"via_drill": 0.5,
"wire_width": 6
} }
], ],
"meta": { "meta": {
@ -437,7 +454,20 @@
}, },
"net_colors": null, "net_colors": null,
"netclass_assignments": null, "netclass_assignments": null,
"netclass_patterns": [] "netclass_patterns": [
{
"netclass": "Power",
"pattern": "+12V"
},
{
"netclass": "Power",
"pattern": "-12V"
},
{
"netclass": "Power",
"pattern": "GND"
}
]
}, },
"pcbnew": { "pcbnew": {
"last_paths": { "last_paths": {

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