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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 16 Latest commits for file Docs/precadsr_layout_front.pdf Panels/dual_vca.scad Normal file View File 3D Printing/Rails/18hp_outie.stl.
- -0.137635 -0.106825 0.984705 vertex -5.12711 5.32461 6.87554.
- 2.0mmx2.0mm inductor taiyo-yuden nr smd Inductor, Taiyo.