X="5.3" y="3.5"/> Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks Finish schematic, add PDF' (#2) from schematic into main ... Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 2_pin_Molex_connector | 2 Panels/futura medium bt.ttf Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.kicad_mod Normal file Unescape Schematics/OttosIrresistableDance/OttosIrresistableDance.kicad_pro Normal file View File Align panel to integer pseudo-origin, remove testing text, decrease title label font so we don't lose it QuentinEF.ttf | Bin 0 -> 510084 bytes // PCB holder main MK_VCO/Panels/Font files/Futura XBlk BT.ttf | Bin 16561 -> 0 bytes Latest commits for file Schematics/SynthMages.pretty/P160_pot_hole_nonpcb.kicad_mod ttrss-plugin- _comics/init.php 342 lines.