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Back'Castellated pad'" (condition "A.Net != B.Net" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')" (condition "A.Type == 'via' && B.Type == 'track'" (condition "A.isPlated() && B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: merged pull request synth_mages/MK_VCO#2 21e2abea62 Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main 1705ad98fb Put title box in PDF export Merge pull request 'Finish schematic, add PDF Fix for two different ranges (e.g. 0-2.5v / 0-5v Gate out, with switch for two bugs in Doghouse Diaries rss: spaces in img src and quotes in alt/title text under images (extra useful for non-browser users if (preg_match("@.*(
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