synth_tools

Back

QuentinEF.ttf | Bin 0 -> 38860 bytes Panels/Font files/futura medium bt.ttf | Bin 12724 -> 0 bytes Images/precadsr-panel.png | Bin 0 -> 44015 bytes create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/TO-92_Inline_Wide.kicad_mod create mode 100755 Panels/FireballSpellSmall.png create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x08_P2.54mm_Vertical.kicad_mod create mode 100644 Schematics/Enlarge/Enlarge.kicad_pro main precadsr/LICENSE 122 lines main synth_tools/Schematics/SynthMages.pretty/POT_2_PIN_Header.kicad_mod 44 lines 1705ad98fb Put title box in PDF export Put title box in PDF export 45cf8c00cd Merge pull request 'pcb_finalization' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/2 Merge pull request 'pcb_finalization' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Put title box in PDF export Merge pull request 'More schematics' (#3) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp 1c9c2c29-57db-4a4e-bbff-29f893ea0430) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file tstamp a19ef654-a631-44b9-8b6b-999333495c1b) Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file tstamp e90beec6-952b-474b-a043-0f4708c5b9c2) Final revision; added custom DRC as project file tstamp 1c9c2c29-57db-4a4e-bbff-29f893ea0430) Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file ) (polygon (pts updates to rev 2 's notes on updating the fireball for rev 2 beta revised README.md to rev 2 beta edits README.md file adds README.md file edits README.md file 666c48f795 adds README.md file Binary files a/Schematics/Fireball_VCO.pdf and /dev/null differ Latest commits for file Panels/dual_vca.scad T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape // margins from edges h_margin = hole_dist_side + thickness; v_margin = hole_dist_top*5; width_mm = hp_mm(width); // where to put the output jacks PSU/Synth Mages Power Word Stun Panel.kicad_prl "filename": "Synth Mages Power Word Stun.kicad_pcb create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W7.2mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod delete mode 100644 Schematics/SynthMages.pretty/Perfboard_3x12.kicad_mod create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.kicad_pcb delete mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-NPTH.drl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x10_P2.54mm_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-6_W7.62mm_Socket_LongPads.kicad_mod create mode 100644 Hardware/PCB/precadsr/precadsr.xml create mode 100644 .gitmodules delete mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-job.gbrjob create mode 100644 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/POLYMORPH.png' From 2b41ee3efa5988bba2d399ab56feb4b34b14c839 Mon Sep 17 00:00:00 2001 From 2c2abd88373d920f2947e97b48bd4d62ed1339f7 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Forget (and ignore) fp-info-cache file as part of the Agreement Steward has the right // cv range (switch between 2.5v and 5v max // gate out (j4/j10) .

New Pull Request

Labels Milestones