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4.784231e-001 8.781294e-001 -0.000000e+000 vertex 3.086953e+000 4.721622e+000 2.496000e+001 vertex 2.260702e-001 7.029575e+000 9.983999e+000 vertex 3.318426e+000 4.564005e+000 1.747200e+001 facet normal 2.121136e-001 -3.654925e-001 9.063239e-001 vertex -8.147030e-001 5.465666e+000 2.491820e+001 facet normal -0.0865373 -0.878615 0.469624 facet normal 0.125325 -0.992116 0 facet normal 0.400414 -0.779905 0.481058 vertex -4.69689 4.43444 7.32632 vertex -0.394998 -6.4137 7.51797 vertex -4.34627 4.86109 7.33259 vertex 0.18558 -6.45682 7.32632 vertex -4.86109 4.34627 7.33259 vertex 4.69689 4.43444 7.32632 vertex -4.86109 -4.34627 7.33259 facet normal 0.0814915 0.0817041 0.993319 vertex 4.58792 -4.29176 7.81747 facet normal 0.900359 -0.423669 0.0992904 vertex 7.43821 2.945 20 facet normal 1.240490e-15 9.755479e-16 -1.000000e+00 facet normal 0.163174 0.820341 -0.548101 facet normal -0.920074 -0.090682 0.381103 facet normal 0.634912 0.772501 0.0113542 facet normal -4.075203e-001 -7.106009e-001 5.735623e-001 vertex 4.315806e+000 3.336501e+000 2.480400e+001 facet normal -0.264267 -0.161938 0.950757 vertex 5.11979 -0.990711 18.9636 vertex 4.51686 -0.737827 18.8084 vertex 4.47758 -0.23878 18.7299 vertex 4.28314 -0.737827 18.8084 vertex 5.00436 0.43909 18.8084 facet normal -0.956942 0.288323 0.0336373 facet normal -0.0463756 0.470888 0.880973 facet normal 0.353624 -0.430898 0.830227 facet normal 9.996004e-01 -2.718511e-03 -2.813611e-02 facet normal 9.342429e-01 3.566373e-01 -2.218012e-04 facet normal -0.904824 -0.425785 0 Latest commits for file Schematics/schematic_bugs_v1.md Update Schematics/schematic_bugs_v1.md Clock POT is too small; need more than 100k to get 1:1 between schematic and PCB, no warnings More work finding space for everything, lining things up more Binary files /dev/null and b/Panels/Font files/futura medium bt.ttf | Bin 0 -> 13714 bytes .../precadsr-panel-Gerbers/precadsr-panel.drl | 47 .../precadsr-panel.gbrjob | 126 .../precadsr-panel/precadsr-panel-cache.lib | 106 .../precadsr-panel-rescue.kicad_sym | 228 .../precadsr-panel/precadsr-panel.kicad_pro | 481 .../precadsr-panel/precadsr-panel.kicad_sch | 831 Hardware/Panel/precadsr-panel/sym-lib-table | 2 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'Put title box in PDF export' (#4) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty .

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