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BackFiles (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= 0d3d72c49e606725216a5a9a4217e6c039d5a574 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c Add schematic, start on PCB 7f9b624c8e tweaks layout with input from sam b0f8ee4ade traces added but maybe won't keep Fireball/Fireball.kicad_prl | 8 "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace Add notes about wiring SW15 cross-board Add notes about UX component wiring 55ee65a5e9 Checkpoint after converting most things to SMD Binary files /dev/null and b/3D Printing/Rails/18hp_innie.stl differ Binary files /dev/null and b/3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels' 0 0 Y N 1 F N DEF SW_Coded_SH-7040 SW 0 0 Y.
- 4.350363e+000 3.396974e+000 2.488700e+001 facet normal.
- -7.536157e-001 4.886994e-001 facet normal -0.734388 -0.325732.
- Hole sizes threeUHeight = 133.35.
- -8.314790e-01 0.000000e+00 vertex -9.019160e+01.
- -7.63602 2.3554 19.9406 facet.