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BackWould make for 7 wires to run, so maybe not. It works this way. "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", From a924f971822abf6232c3be63abeee0abf33f42cb Mon Sep 17 00:00:00 2001 Add VCA shaek layout Add schematic, start on PCB Added input resistor for sync; placed everything on PCB 7f9b624c8e tweaks layout with input from sam 7f9b624c8e1f1f65b5263dc5de76990cc9e84778 scale([.38,.38,-.005]) surface("FireballSpellVertSmaller.png", center=true, invert=false); } module make_surface(filename, h) { } module make_surface(filename, h) { wants to merge 3 commits » c971d0bd8b Merge pull request synth_mages/MK_VCO#2 merged pull request 'Fix rail clearance issues, make all power traces large From 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Mon Sep 17 00:00:00 2001 Panels/FIREBALL VCO.png Normal file View File 3D Printing/Cases/Eurorack 2-Row/2row_frame.scad Executable file Unescape Schematics/Unseen Servant/Unseen Servant.kicad_pcb | 4 .../PCB/precadsr_aux_Gerbers/precadsr-PTH.drl | 99 .../precadsr_aux_Gerbers/precadsr-job.gbrjob | 128 .../precadsr_panel_al.kicad_pcb | 2707 .../Bigger_Push_Switch_Hole.kicad_mod | 17 .../precadsr_panel_al/precadsr_panel_al.sch | 264 .../Panel/precadsr_panel_al/sym-lib-table | 4 .../PCB/precadsr_Gerbers/precadsr-PTH.drl | 207 .../PCB/precadsr_Gerbers/precadsr-job.gbrjob | 2 | | C1 | 1 | Conn_01x07 | *(optional) SIP socket, 2.54 mm, 1x10 Pin socket, 2.54 mm, 1x10 | | | C2, C5, C6, C8, C9 | 4 .../PCB/precadsr_Gerbers/precadsr-B_Paste.gbr | 15 .../precadsr_aux_Gerbers/precadsr-F_SilkS.gbr | 2066 .../precadsr_aux_Gerbers/precadsr-NPTH.drl | 4 | | | | | Tayda | A-804.
- Normal 9.039176e-001 4.795500e-003 4.276799e-001 facet.
- -0.0555529 0.705985 vertex 6.47823 0 19.4867.
- Round THT pads Net.