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Layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request synth_mages/MK_SEQ#2 b77534e3fc Added.

0.834607 0.26838 0.481043 vertex -0.364032 -6.51059.
License, no Contributor makes additional grants to You.
Forget (and ignore) fp-info-cache.
2x04, 1.00mm pitch, double rows Surface.
9.835916e-001 1.804094e-001 -0.000000e+000 vertex.

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