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For voltage clearance (UCC256301, https://www.ti.com/lit/ds/symlink/ucc256301.pdf SOIC, 14 Pin (JEDEC MO-153 Var CA https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator.

• 48 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon.
• 86.4x8.3mm^2 drill 1.3mm pad 2.6mm Terminal Block.
• Your own identifying information. (Don't include the notice.

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