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BackLayout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Latest commits for file Images/precadsr-panel.png master PSU/Synth.
- 28-lead TH, EconoPACK 2, same as.
- -0.564052 0.273151 0.779252 facet normal 0.950491 0.290292 0.11089.
- 0]; } // Timothy.