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Ref="R29" Part="1" AR Path="/607ED812/60970E37" Ref="S3" Part="1" AR Path="/60A9C088" Ref="R?" Part="1" AR Path="/609384DB" Ref="#FLG?" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG03" Part="1" AR Path="/60C3833D" Ref="R?" Part="1" AR Path="/60B160FF" Ref="J?" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG0102" Part="1" AR Path="/607ED812/60802B98" Ref="R29" Part="1" AR Path="/607ED812/60C38343" Ref="R22" Part="1" From 3d279dd88cba890e1ff05b6fd01cb5480b1f325e Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 Align panel to integer pseudo-origin, remove testing text.

Https://www.vishay.com/docs/95214/fto218.pdf TO-218-2 Horizontal RM 1.7mm Pentawatt Multiwatt-5 staggered.
-0.137635 0.984705 facet normal -0.468298.
-5.54018 4.83492 6.98312 vertex 5.5107 -4.61666.

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