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BackUnescape Hardware/PCB/precadsr/ao_tht.pretty/D_DO-41_SOD81_P7.62mm_Horizontal.kicad_mod Normal file View File 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/COLOR SPRAY.png' abc39a50d6 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/FIREBALL VCO.png create mode 100644 Panels/title_test.scad From 16c50fa0a87ddc27dfbf2c780c81516736a5bb00 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update README.md 40588ba725f2f6c7240cc5d95c2a8af539e27e15 Update README.md * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How to use Images/adsr.png | Bin 0 -> 44015 bytes create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-PTH.drl create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Pot_Hole.kicad_mod delete mode 100644 Panels/a_color_icon_of_a_flying_fireball.webp create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Switch_Hole.kicad_mod create mode 100644 3D Printing/Pot_Knobs/potentiometre_v3_1.5_merged.stl Normal file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-MaskBottom.gbs Normal file View File Panels/Font files/futura medium condensed bt.ttf differ From e825437e5db64d4ef13181f883b9fe719cf4c2a1 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Move LED resistors .../Unseen Servant/Unseen Servant.kicad_pro Normal file View File 3D Printing/Cases/Eurorack Modular Case/DSC03778.JPG Executable file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-PTH.drl Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x08_P2.54mm_Vertical.kicad_mod Normal file View File 3D Printing/Cases/Eurorack 2-Row/4c327a694daeb206e2eed537a2001b91_preview_featured.jpg Executable file View File Latest commits for file Datasheets/2N3903-Motorola.pdf # Autorouter files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Synth_Manuals/VALMORIFICATION+Build+and+BOM.pdf Normal file View File Panels/FireballSpell_Large_bw.xcf Executable file View File Panels/luther_triangle_10hp.scad Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-job.gbrjob Normal file View File Merge pull request 'Fix rail clearance issues, make all power traces large Fireball/Fireball.kicad_pro | 4 | 100nF | Unpolarized capacitor | | | S1 | 1 | SW_3PDT_x3 | Switch, triple pole double throw, separate symbols"/>
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