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ZAV S-PBGA-N289 Texas Instruments, DSBGA, 0.822x1.116mm, 5 bump 2x1x2 array, NSMD pad definition Appendix A BGA 484 0.8 RS484 Artix-7 BGA, 19x19 grid, 10x10mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 UCBGA-81, 9x9 raster, 4.4084x3.7594mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf WLCSP-81, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; http://www.fujitsu.com/global/documents/products/devices/semiconductor/fram/lineup/MB85RS1MT-DS501-00022-7v0-E.pdf Infineon LFBGA-292, 0.35mm pad, 17.0x17.0mm, 292 Ball, 20x20 Layout, 0.8mm Pitch, https://www.ti.com/lit/ml/mpbg777/mpbg777.pdf BGA 289 0.8 ZAV S-PBGA-N289 Texas Instruments, DSBGA, 1.4715x1.4715mm, 9 bump 3x3 array, NSMD pad definition Appendix A Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=304, NSMD pad definition (http://www.ti.com/lit/ds/symlink/msp430f2234.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf Texas Instruments, DSBGA, area grid, NSMD pad definition Appendix A Artix-7 BGA, 19x19 grid, 10x10mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.35mm; https://datasheets.maximintegrated.com/en/ds/MAX40200.pdf WLP-9, 1.448x1.468mm, 9 Ball, 3x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l412t8.pdf ST WLCSP-49, off-center ball grid, ST die ID 456, 1.94x2.4mm, 20 Ball, 4x5 Layout, 0.4mm Pitch, https://www.ti.com/lit/ml/mxbg419/mxbg419.pdf, https://www.ti.com/lit/ds/symlink/tmp117.pdf Texas Instruments, DSBGA, 3.33x3.488x0.625mm, 49 ball 7x7 area grid, YZT, 1.86x1.36mm, 12 Ball, 4x3 Layout, 0.4mm Pitch, https://pdfserv.maximintegrated.com/package_dwgs/21-100489.PDF WLCSP-25, 5x5 raster, 2.423x2.325mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.8mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f301r8.pdf WLCSP-49, 7x7 raster, 2.965x2.965mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/DM00257211.pdf WLCSP-64, 8x8 raster, 4.466x4.395mm package, pitch 0.8mm TFBGA-121, 11x11 raster, 10x10mm package, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf LFCSP VQ, 48 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py 8-Lead Plastic PSOP, Exposed Die Pad (see https://www.diodes.com/assets/Package-Files/SO-8EP.pdf 20-Lead Plastic Quad Flatpack (PF) - 14x14mm body, 9.5mm sq thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8800.pdf HTSSOP, 16 Pin (http://www.ti.com/lit/ds/symlink/lmh0074.pdf#page=13), generated with kicad-footprint-generator Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-138 , 8 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py eSIP-7C Vertical Flat Package with Heatsink Tab https://ac-dc.power.com/sites/default/files/product-docs/linkswitch-ph_family_datasheet.pdf SIP4 Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf) following land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl225.pdf Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-230, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf Footprint for Mini-Circuits case MMM168, Land pattern PL-094, pads 5 and 6); middle of panel after deducting left/right sub-panels slider_center = (width_mm - left_panel_width - right_panel_width)/2 + left_panel_width; slider_bottom = v_margin+12; row_2 = row_1 + v_margin + 12; top_row = height - rail_clearance - thickness*2 - 16.5/2; // 16.5 is the main (cylindrical or conical) shape. [mm.

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