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BackGlide, manual (A100k) (two left pins, from below) - Clock POT is the decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock signal, start/stop, manual step (sw13 // 1 hp from side to center of hole, with a diode matrix to select segments from each step. Binary files /dev/null and b/Panels/luther_triangle_vco_quentin_v3_blank.stl.stl differ Binary files /dev/null and b/Panels/FireballSpellSmall.png differ Binary files /dev/null and b/Panels/Font files/futura medium bt.ttf and /dev/null differ main synth_tools/Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod 42 lines synth_tools/PCB Notes.txt 17 lines Notes from debugging aac0a4a5b4f604add3c1ccb9d39a8956f2d60f00 More notes Schematics/schematic_bugs_v1.txt | 2 | 1N5817 | Schottky Barrier Rectifier Diode, DO-41"/>