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Normal -3.472752e-15 -2.508470e-15 1.000000e+00 facet normal 9.527700e-01 3.036929e-01 0.000000e+00 vertex -9.539322e+01 1.058130e+02 1.855000e+01 vertex -1.008637e+02 1.051965e+02 1.055000e+01 vertex -1.040802e+02 9.627468e+01 2.550000e+00 facet normal 0.767777 0.634425 0.0895734 facet normal 0.288937 -0.749604 0.59549 facet normal 0.584886 -0.805022 0.0992381 facet normal -0.982268 -0.187482 0 vertex 8.65691 5.31736 2.19603 vertex 3.87041 -9.34401 2.58057 facet normal -0.920081 0.0458278 0.389038 facet normal -0.223441 0.736595 -0.638358 vertex 1.17054 5.88471 6.59 facet normal 0.916108 0.277897 0.288995 facet normal 6.453925e-02 2.878077e-03 -9.979110e-01 facet normal 0.288281 -0.956957 0.0335834 vertex 5.51437 1.05741 21.6407 facet normal -2.304122e-004 -4.032215e-004 -9.999999e-001 Latest commits for file Images/PXL_20210831_000922493.jpg 4579d541a8 Adding SynthMages footprint library create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_SilkS.gbr create mode 100644 Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Push_button_A-5050.kicad_mod create mode 100644 Synth Mages Power Word Stun.kicad_sch 3736 lines Latest commits for file Schematics/Luthers_VCO_schematic.pdf Subject: [PATCH] Initial version *.bck New KiCad version; non Al panel Gerbers # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Examples/EG_MANUAL.pdf schematic start, and some example modules 811ef45c764021f623b8bb59234df1314fce4e91 12V, -12V and ground needed, probably up.

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