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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Minor layout tweaks.
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- Width 16.90 mm Power-Integrations variant.
- -9.289982e+01 1.045249e+02 3.455000e+01 facet normal -0.343415 0.685181.