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Report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 26933738 bytes SNARE_MANUAL.pdf | Bin 0 -> 461484 bytes Panels/title_test_36.stl | Bin 0 -> 1303306 bytes Panels/FireballSpellVertSmall.png | Bin 0 -> 31010 bytes Panels/label_test.stl.

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