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2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks From cd915e24c94d463c67b0b011c09a1ed6f99bb0bf Mon Sep 17 00:00:00 2001 Subject: [PATCH] SVG decontamination Hardware/Panel/precadsr_panel.svg | 4 | 100nF | Unpolarized capacitor | | | J9 | 1 uF | Polarized capacitor | | C9 | 4 | 1M | Resistor | | | | D3, D4, D5, D6, D7, D8, D9, D10 Standard switching diode, DO-35"/> 6.92908 -2.87013 6.0001 vertex -6.23601 -4.16678 6.0001.

  • 1.05962 7.92322 facet normal -5.964241e-001 8.026695e-001.
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