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Submitted to fab on 2024/01/24. From b11a8d31874f2e074879a668b4f6eb5f32915bd6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] schematic start, and some example modules Envelope/Envelope.kicad_pcb | 2 | 1nF | Film capacitor | | | S2 | 1 | B20k | Potentiometer | | D1, D2, D3, D4, D5, D8, D9, D10 | 8 pin SIM connector for 1.6mm PCB's with 60 contacts (polarized Highspeed card edge connector for 2.4mm PCB's with 30 contacts (not polarized Highspeed card edge card connector socket for 2.36mm PCBs, vertical, alignment pins (source: https://suddendocs.samtec.com/prints/hsec8-1xxx-xx-xx-dv-x-xx-footprint.pdf 0.8 mm BGA-64, 10x10 raster, 4.618x4.142mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, 27.0x27.0mm, 756 Ball, 32x32 Layout, 0.8mm Pitch, https://www.ti.com/lit/ml/mpbg777/mpbg777.pdf BGA 289 0.8 ZAV S-PBGA-N289 Texas Instruments, DSBGA, area grid, YBG pad definition, 0.95x1.488mm, 6 Ball, 2x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32u575og.pdf#page=306 ST WLCSP-100, ST die ID 483, 3.73x4.15mm, 115 Ball, X-staggered 13x8 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g431c6.pdf ST WLCSP-49, off-center ball grid, ST die ID 479, 3.56x3.52mm, 64 Ball, 8x8 Layout, 0.4mm Pitch, https://www.nxp.com/docs/en/package-information/SOT1963-1.pdf ST.

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