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BackKiCad # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files fp-info-cache # Netlist files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md 8be0bd80e05e7fe62720d7fda27423a4c75b90a3 Update README.md 8be0bd80e05e7fe62720d7fda27423a4c75b90a3 Update README.md 40588ba725f2f6c7240cc5d95c2a8af539e27e15 Update README.md 5505000471ab249f70d985a8f814bce077fb47b2 Update README.md 2cb8e5eaf679e30139948d8744800b04487466fc updated C5 footprint & tracing; schematic annotation 2cbdb94ba94f485ce4abcb1f14e2e5f15d016647 updates the potentiometer pads and trace routing to de-bodge the pots. 's notes on repique/caixa, two or three for surdos