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Back== 'via' && B.Type == 'track'" (condition "A.Type == 'track' && B.Type == 'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W7.2mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod Normal file Unescape Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Mounting_Hole.kicad_mod Normal file Unescape // pots (all p160s): font_for_label = "Futura Md BT:style=Medium"; STLs, 10hp version, others schematics Replaced accidentally dropped Fine tuning hole. Latest commits for file Schematics/schematic_bugs_v1.md Update Schematics/schematic_bugs_v1.md more fixes
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