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Back"Notes": "Layers L1/L2" "Notes": "Layer F.Mask" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request synth_mages/MK_VCO#7 Updates from real TL0x4s d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground.
- Normal 2.848627e-15 -5.571352e-15 1.000000e+00 facet normal 0.106559.
- /arrasta/commit/531ebcae92ad8ad00635060e3583259ee13cc12b">531ebcae92ad8ad00635060e3583259ee13cc12b 2bb058d5715f395d3571ea05d3008566787a2bdb