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"vrml": "" }, "schematic": { "annotate_start_num": 0, "drawing": { More tweaks after pro review "different_unit_footprint": "error", "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", More tweaks after pro review Apply jlcpcb's design rules, small fixes for those couple more minor clearance tweaks couple.

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