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Back-> 163520 bytes Images/IMG_6777.JPG | Bin 0 -> 29479 bytes .../VALMORIFICATION+Build+and+BOM.pdf | Bin 0 -> 328607 bytes Images/PXL_20210831_001017829.jpg | Bin 0 -> 193665 bytes Images/precadsr-panel.png | Bin 0 -> 27618364 bytes create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-B_Paste.gbr create mode 100644 Hardware/PCB/precadsr/sym-lib-table create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/SolderWirePad_1x01_Drill0.8mm.kicad_mod create mode 100644 Schematics/SynthMages.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_Shaft_Centered.kicad_mod create mode 160000 Hardware/lib/aoKicad create mode 100644 3D Printing/Panels/HOLD PORTAL.png create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x08_P2.54mm_Vertical.kicad_mod create mode 100755 Panels/FireballSpell_Large_bw.png create mode 100644 Envelope/Envelope.kicad_pro create mode 100644 3D Printing/Pot_Knobs/pot_knob_two_parts_base.stl Normal file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-MaskTop.gts Normal file View File main precadsr/.gitignore 58 lines # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 1/2] Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces One SPST switch per step, to enable/disable gate per the Eurorack standard Outputs saw, triangle, and square waves, with CV control of pitch and FM modulation, hard sync, and pulse wave modulation (PWM). Hard controls include coarse and +12V, value unknown 5a4e89eea63bf71c8fd68e1168f096dfb3459aa4 More cleanup d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 Align panel to integer pseudo-origin, remove testing text, decrease title.
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