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Back*.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= 14162964f93e8c9aadec1d2edfbf49ea0b8bcb52 Add Kick as separate sheet wants to merge 3 commits » 33729ec97f More repo cleanup, adopt github .gitignore file .gitattributes | 2 Smaller cap (476nF?) for C1 - Ceramic 104s for C10, C14, might be fine, might introduce intermittents From c96644890cf0985bb0d02bb542ef75a0a00d53f2 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More schematics Merge pull request 'Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 Component Count: 74 Refs C6, C7, C8, C9 Schottky Barrier Rectifier Diode, DO-41"/>
- In pads, 2 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf.
- Printing/Pot_Knobs/scaled_french_pot.mix differ Binary files /dev/null and b/3D.