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BackCondition "A.Net != B.Net" condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == A.Type && A.Net != B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_Cu.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/SolderWirePad_1x01_Drill1mm.kicad_mod Normal file Unescape Hardware/Panel/precadsr-panel/fp-lib-table Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_Mask.gbr Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pretty/precadsr-panel-art.kicad_mod Normal file View File 3D Printing/Pot_Knobs/Pot3.STL Executable file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-EdgeCuts.gm1 Normal file.
- Diameter=8.0mm, Tantal Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf.
- Http://rohmfs.rohm.com/en/products/databook/datasheet/ic/motor/dc/bd621x-e.pdf SC-59, hand-soldering varaint, https://lib.chipdip.ru/images/import_diod/original/SOT-23_SC-59.jpg.
- 0.108199 facet normal 5.724839e-01.