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Back-4.248064e-01 facet normal -0.392055 -0.2628 0.881606 facet normal 0.989348 0.0974089 0.108177 facet normal -0.277899 -0.916108 0.288996 vertex -8.79978 -1.75038 4.79464 facet normal 9.017105e-001 4.415479e-003 4.323179e-001 facet normal -0.022139 0.096999 -0.995038 vertex -4.25372 9.04499 0.0456265 facet normal -0.365098 -0.683048 0.632574 facet normal 0.539147 0.334131 0.773096 vertex 6.71529 -0.463226 7.17947 vertex -6.8561 0.38016 7.04537 vertex 6.81829 0.589577 7.19149 vertex -6.85859 -0.790944 7.37319 facet normal -0.77301 -0.634394 1.15672e-06 facet normal 1.120389e-15 6.002714e-16 -1.000000e+00 facet normal -0.995114 -0.0980109 -0.0119198 facet normal 0.587776 0.809024 0 facet normal -4.064179e-001 -7.112316e-001 5.735627e-001 facet normal 3.766283e-14 -1.000000e+00 -5.402816e-14 facet normal 0.678848 -0.362852 -0.63836 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository https://github.com/holmesrichards/precadsr Submodules Latest commits for file Panels/dual_vca.scad T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are.
- (https://docs.broadcom.com/docs/AV02-0169EN SOIC 1.27 16 12 Wide.
- -4.325091e-001 7.407266e-001 5.140622e-001 facet normal -0.95681 0.29047 -0.0119413.