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BackR11 | 3 From afea9d5a2cf23e2a33a2927086270d4d602f5a2b Mon Sep 17 00:00:00 2001 Subject: [PATCH] Correcting changed filename in .prl gets jiggy with PCB locator, 8 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing⟨=en&documentid=0000992393), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 64 Pin (www.intel.com/content/www/us/en/ethernet-controllers/i210-ethernet-controller-datasheet.html), generated with kicad-footprint-generator JST XH series connector, LY20-16P-DLT1, 8 Circuits (https://www.molex.com/pdm_docs/sd/2005280080_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TQFP, 48 Pin (http://ww1.microchip.com/downloads/en/devicedoc/00002117f.pdf#page=69), generated with kicad-footprint-generator JST XH series connector, SM08B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf.
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