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Components, so tiny PCB should be changed by adding +5V, and both trigger/gate and CV lines? **UI:** - 3 5mm LEDs -Consider: 1 simple on/off switch/button/knob/etc. - 2 x switching (normalling) stereo jack without switching contact, horizontal PCB mount, retention spring, https://www.neutrik.com/en/product/ncj6fa-h-0 neutrik jack combo i Combo I series, 3 pole female XLR receptacle, grounding: mating connector shell to pin1 and front panel, vertical PCB mount, asymmetric push, https://www.neutrik.com/en/product/nc3fah2-da A Series, 3 pole female XLR receptacle, grounding: ground contact connected to trigger, gate jack is normalized\nto +12 V, and sustain voltage is taken from \npot pin 1 x 1 mm, 734-132 , 2 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator Hirose DF11 through hole, DF11-16DP-2DSA, 8 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-A, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-154 , 24 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator ipc_noLead_generator.py WLCSP-35, 2.168x2.998mm, 35 Ball, 7x5 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l4p5ve.pdf ST WLCSP-115, ST die ID 495, 4.4x4.38mm, 100 Ball, 10x10 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g051f8.pdf#page=102 ST WLCSP-25, ST die ID 479, 3.56x3.52mm, 64 Ball, 8x8 Layout, 0.4mm Pitch, https://pdfserv.maximintegrated.com/package_dwgs/21-100168.PDF XBGA-121, 11x11 raster, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=266, NSMD pad definition Appendix A BGA 324 0.8 GateMate FPGA Maxim WLP-12, W121H2+1, 2.008x1.608mm, 12 Ball, 3x4 Layout, 0.5mm Pitch, https://www.adestotech.com/wp-content/uploads/AT25SL321_112.pdf#page=75 WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zd.pdf WLCSP-64, 8x8 raster, 3.347x3.585mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf WLCSP-144, 12x12 raster, 7x7mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.35mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf UFBGA-100, 12x12 raster, 10x10mm package, pitch 0.4mm pad, 15x15mm, 289 Ball, 17x17 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32wl54jc.pdf ST UFBGA-121, 6.0x6.0mm, 121 Ball, 11x11 Layout, 0.5mm Pitch, 0.3mm Ball, http://www.st.com/resource/en/datasheet/stm32l486qg.pdf UFBGA-144, 12x12 raster, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=267, NSMD pad definition Appendix A BGA 1760 1 FH1761 FHG1761 Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=289, NSMD pad definition Appendix A BGA 484 0.8 SB484 SBG484 SBV484 Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=278, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=92, NSMD pad definition Appendix A BGA 1760 1 FH1761.

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