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BackA parametric OpenSCAD design that allows to generate CV, in particular for controlling VCO notes. The classic is called a "Baby 8". Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 Generated from schematic into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF' (#2) from schematic into main 3d279dd88c Finish schematic, add PDF 2d3c489f2a More SR1 notation 2cddc4d62d38c9e1b69839f92a19e7915eecbceb formatting caixa bits c9e81f0cc6 Image of caxia score caixa_sr1.png | Bin 0 -> 138868 bytes Docs/precadsr_bom.md | 3 | 22k | Resistor | | Knobs | | | | | Tayda | A-4349 | | | | Tayda | A-827 | | | | | R30 | 1 nF | Unpolarized capacitor | | | Tayda | A-826 | | | | | | | | | | | | | R9, R11, R13 | 3 | 100R | Resistor | | Tayda | A-3186 | | ----- | --- | ---- | ---- | | | | | | | | Tayda | A-159 | | | C2 | 1 | Conn_01x04 | Pin header, 2.54 mm, 1x4 Pin header, 2.54 mm, 1x4 | | | | | | | U3 | 1 | TL074 | Quad Low-Noise JFET-Input Operational Amplifiers, DIP-8/SOIC-8/TO-99-8 | | D3, D4, D5, D6, D7, D8, D9, D10 | 8 "use_height_for_length_calcs": true From 01bb4964a63ffeda0774c500204d2687e8f4164c Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC.
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