Labels Milestones
Back6.25mm package, pitch 0.8mm; http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#p495 TFBGA-216, 15x15 raster, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=260, NSMD pad definition Appendix A BGA 1156 1 RF1157 RF1158 Virtex-7 BGA, 42x42 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=278, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=92, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0104.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf Texas Instruments, DSBGA, area grid, YBJ0008 pad definition, 0.95x1.488mm, 6 Ball, 2x3 Layout, 0.4mm Pitch, YFF0006, NSMD pad definition Appendix A BGA 324 0.8 CS324 CSG324 BGA 324 0.8 CSGA324 Artix-7, Kintex-7 and Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A BGA 324 0.8 CSGA324 Artix-7, Kintex-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=276, NSMD pad definition Appendix A BGA 225 0.8 CLG225 Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=297, NSMD pad definition Appendix A Artix-7 BGA, 19x19 grid, 10x10mm package, pitch 0.4mm pad, 15x15mm, 289 Ball, 17x17 Layout, 0.8mm Pitch, https://www.st.com/resource/en/datasheet/stm32mp151a.pdf ST UFBGA-73, 5.0x5.0mm, 73 Ball, 9x9 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stulpi01a.pdf TFBGA-64, 8x8 raster, 4.539x4.911mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-144, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on either internal or external clock sources cycle between 0v and 5v max // gate out (j4/j10) // clock in (j2/j11) // casc out (j14/j15 // reset/casc in (j1/j13) // gate out (j4/j10 // clock in (j2/j11) // casc out (j14/j15) // reset/casc in (j1/j13 // gate out // cv range (sw12 // steps: slider, led, switch (sw1-sw10, rv1-rv10 // mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 9-pin D-Sub connector straight vertical THT male pitch 2.41x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 63.5mm mounting-hole-offset.
- 7.266719e-01 -1.535527e-04 facet normal -0.705398 -0.0694843 0.705398 0.705398.
- -3.927162e-01 vertex -1.052606e+02 9.695134e+01.