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B/Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-drl_map.pdf differ eea453f1ee Go to file b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane Latest commits for file caixa_sr2.png Fix sr2 blue 2cddc4d62d formatting caixa bits caixa_sr1.png | Bin 0 -> 2506984 bytes Panels/title_test.scad | 27 Panels/title_test.stl | Bin 0 -> 16561 bytes create mode 100644 Hardware/PCB/precadsr/precadsr.cmp create mode.

• Taken from \npot pin 1.
• Vertex -1.239765e-001 7.031019e+000 2.496000e+001.
• 2.54mm 11.43mm 450mil SMDSocket LongPads.

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