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BackHttp://www.st.com/resource/en/datasheet/stm32f429ng.pdf WLCSP-143, 11x13 raster, 4.539x5.849mm package, pitch 0.8mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00257211.pdf WLCSP-49, 7x7 raster, 3.141x3.127mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f405og.pdf WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf WLCSP-143, 11x13 raster, 4.521x5.547mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213 Lattice caBGA-756, ECP5 FPGAs, based on SIP7, http://power.murata.com/data/power/ncl/kdc_nma.pdf Isolated 1W DCDC-Converter, http://power.murata.com/data/power/ncl/kdc_nma.pdf Murata NMAxxxxSC footprint based on https://www.analog.com/media/en/technical-documentation/data-sheets/199399fc.pdf TO-92 2-pin variant by Heraeus, drill 0.75mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot371-1_po.pdf STC SOP, 16 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12858&prodName=TLP291-4), generated with kicad-footprint-generator ipc_noLead_generator.py WSON-10 package 2x3mm body, pitch 0.5mm, see http://www.ti.com/lit/ds/symlink/tps62177.pdf WSON 0.5 thermal vias in pads, 6 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator Samtec HLE .100" Tiger Beam.
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