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BackFn, rn [ ord*cos(lf0), ord*sin(lf0), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ird*cos(lf2), ird*sin(lf2), h1], [ ord*cos(lf0), ord*sin(lf0), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ord*cos(lf1), ord*sin(lf1), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Panels/FireballSpellVertSmaller.png (min_thickness 0.25) (filled_areas_thickness no Latest commits for file Synth Mages Power Word Stun.kicad_pro", Latest commits for file Fireball/Fireball_panel.kicad_pro Latest commits for branch hard_sync Merge pull request synth_mages/MK_SEQ#2 Added schmancy pcb.
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