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2.423x2.325mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 UCBGA-49, 7x7 raster, 3.89x3.74mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf UFBGA 132 Pins, 0.5mm Pitch, https://ww1.microchip.com/downloads/en/DeviceDoc/16B_WLCSP_CS_C04-06036c.pdf WLCSP-20, 4x5 raster, 1.934x2.434mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf UFBGA-201, 15x15 raster, 10x10mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm pad, based on the larger board underneath the smaller board. #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net" condition "A.Type == 'via' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'pad' && B.Type == A.Type")) # 4-layer condition "A.Type == 'track'" (condition "A.isPlated() && B.Type == A.Type" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Type == 'pad' && B.Type .

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