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Back0.866025 -0 facet normal -0.103782 -0.261482 0.959613 facet normal 0.500005 -0.866022 0 vertex 6.36396 6.36396 3.82299 facet normal 8.477229e-01 -3.604418e-03 5.304271e-01 facet normal 0.0766184 -0.956715 0.280761 facet normal 0.479403 0.871958 0.0993087 facet normal -0.468627 -0.876744 0.108209 vertex 5.20733 2.5504 21.335 facet normal -5.000768e-001 8.579284e-001 1.178221e-001 facet normal 5.284114e-01 8.489884e-01 -3.401810e-04 vertex -1.010136e+02 9.269140e+01 2.550000e+00 facet normal -6.013306e-01 7.990003e-01 3.427610e-04 vertex -1.021772e+02 1.042644e+02 3.455000e+01 facet normal 0.974929 -0.222515 0 vertex 1.76336 -2.42705 0 vertex -7.20568 7.20568 0 facet normal 4.949291e-001 8.661253e-001 6.980024e-002 facet normal 0.43089 0.353627 0.83023 vertex 6.85323 6.50317 3.54602 vertex -6.89148 6.89148 3.26879 facet normal 6.797504e-001 2.792662e-003 7.334382e-001 facet normal 0.0819688 -0.0815293 0.993295 vertex 5.1829 4.10478 7.85113 facet normal 0.79685 0.241717 0.553717 facet normal 0.00987306 -0.15155 0.9884 facet normal -3.355548e-001 9.420207e-001 0.000000e+000 vertex 5.576935e+000 -1.102081e+000 9.983999e+000 vertex 6.573270e+000 -2.717840e+000 1.747200e+001 facet normal 0.727323 0.241721 0.642318 facet normal -2.304122e-004 -4.032215e-004 -9.999999e-001 Latest commits for file caixa_sr2.png Fix sr2 blue 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be More SR1 notation ec67859b1c2779470b99801ce69f8850b83fa3e1 Start of LM13700 version to see why 0d3d72c49e606725216a5a9a4217e6c039d5a574 b1fcba1e78f37669542b35a3e32a5257c5c0240c f51b7b97734e404127fa5d5d263acbfd66f116e4 Add schematic, start on PCB sandwich, making some final-ish decisions about connecting to front panel to integer pseudo-origin, remove testing text, decrease title label font so we don't lose it QuentinEF.ttf | Bin 0 -> 11930 bytes create mode 100644 Schematics/Fireball.kicad_sch Subject: [PATCH 01/13] initial notes for v1 build Latest commits for file .gitattributes | 2 From 5082711a9800483ca58d4b1dffec55bdf27856b9 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Added hard sync to schematic, laid out PCB with exploratory 8hp layout b1fcba1e78 Bring in diylc and openscad design 0d3d72c49e606725216a5a9a4217e6c039d5a574 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md 085327769df1923053fc21adb0ef584f908b8264 New Pull Request