Y="2.4"/> Update luther's layout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 0 Minor layout tweaks merged pull request 'Put title box in PDF export' (#4) from schematic into main Merge pull request synth_mages/MK_VCO#3 From 3d0ca7fdf6e2ad8d7864221e585c668e46544055 Mon Sep 17 00:00:00 2001 .../UNSEEN SERVANT.png | Bin 10724 -> 0 bytes From cb59d1e9c06865f5bebe8c7ee0afa4859e0766b2 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More random files main MK_SEQ/Schematics/Unseen Servant/Unseen Servant.kicad_sch | 864 Schematics/Unseen Servant/fp-info-cache Normal file Unescape Fireball/Fireball.kicad_pro Normal file Unescape Synth Mages Power Word Stun.kicad_pro | 85 cd18ed43dc Added hard sync to schematic, laid out PCB with on-board components Add correct footprints to fireball Merge pull request 'More schematics' (#3) from schematic into main ... Finish schematic, add PDF Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 11916 bytes .../Panels/MIRROR IMAGE.png | Bin 0 -> 167187 bytes Images/PXL_20210831_002553634.jpg | Bin 0 -> 144834 bytes .../Pot_Knobs/pot_knob_two_parts_cap.stl | Bin 0 -> 138868 bytes Docs/precadsr_bom.md | 3 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92"/>
Normal -0.0635194 0.807211 0.586836 vertex 4.46118.