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UFBGA-201, 15x15 raster, 13x13mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf WLCSP-64, 8x8 raster, 3.357x3.657mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f378vc.pdf WLCSP-72, 9x9 raster, 3.693x3.815mm package, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf LFCSP VQ, 48 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SS)-5.30 mm Body [DFN] (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF DD Package; 8-Lead Plastic Dual Flat No Lead Package (MC) - 2x3x0.9 mm Body (see Atmel Appnote 8826 10-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_18_05-08-1778.pdf DFN20, 6x5, 0.5P; CASE 506CM (see ON Semiconductor Micro8 (Case846A-02): https://www.onsemi.com/pub/Collateral/846A-02.PDF PSOP44: plastic thin shrink small outline package http://www.ti.com/lit/ds/symlink/drv8301.pdf HVSSOP, 10 Pin (http://rohmfs.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator/bd8314nuv-e.pdf (Page 20)), generated with kicad-footprint-generator ipc_plcc_jLead_generator.py PLCC, 32 Pin (https://www.ti.com/lit/ds/symlink/bq25703a.pdf#page=90), generated with kicad-footprint-generator Soldered wire connection with double feed through strain relief, for a VC version. ** not a jellybean, so $3/ea for sketchy NOS on amazon.

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