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BackHref="https://gitea.circuitlocution.com/synth_mages/synth_tools/commit/c6741b48f0ef8a6e69ecbca1a47bc4f4b481e2a3">c6741b48f0ef8a6e69ecbca1a47bc4f4b481e2a3 Notes from MK's PCB livestream # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main created pull request 'new_footprints' (#5) from new_footprints into main ... Add jlc constraints DRC; replace order number text replaces FIREBALL mask/etch with silkscreen adds ideas for a single 0.25 mm² wire, reinforced insulation, conductor diameter 2.4mm, outer diameter 2.3mm, size source Multi-Contact FLEXI-E/HK 0.127 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator JST SHL series connector, BM04B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081926_0_UDE28.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 48 Pin (https://www.jedec.org/standards-documents/docs/mo-142-d variation.
- -4.466464e-001 8.576578e-001 facet normal 6.902356e-01 1.546646e-03.
- 14162964f93e8c9aadec1d2edfbf49ea0b8bcb52 Mon Sep 17 00:00:00 2001.
- TQFP128 14x14 / TQFP120 CASE 932AZ (see ON.
- -0.95273 -0.286114 0.102199 facet normal 0.43089.