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Back\#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape 3D Printing/Pot_Knobs/scaled_french_pot.mix Normal file View File Hardware/PCB/precadsr_Gerbers/precadsr-Edge_Cuts.gbr Normal file View File Hardware/PCB/precadsr/precadsr.kicad_sch Normal file Unescape Period: 3.
- 0.680175 -0.733049 0 vertex.
- -2.096560e-001 -3.668982e-001 9.063278e-001 facet normal 0.012304 0.156322.