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04 avril 2015 11:21:18 UTC update=Tue 20 Apr 2021 12:09:41 PM EDT Generated from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main Merge pull request 'Fix rail clearance issues, make all power traces large From 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Mon Sep 17 00:00:00 2001 Subject: [PATCH] Correcting changed filename in .prl Correcting changed filename in .prl Correcting changed filename in .prl gets jiggy with PCB locator, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py 6-Lead Plastic Small Outline (SS)-5.30 mm Body (see Atmel Appnote 8826 10-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [QFN]; (see Microchip datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf MLF, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20%20Lead%20VQFN%203x3x0_9mm_1_7EP%20U2B%20C04-21496a.pdf), generated.

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