3
1
Back

Finishes: 43045-220x), 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator JST SUR series connector, SM15B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py PowerPAK 1212-8 Single Zetex, SMD, 8 pin DIP socket A-001 1 14 pin DIP socket A-004 4 Knobs Screws, nuts, and spacers (see build notes) 1 SIP socket, 2.54 mm, 1x10 Pin socket, 2.54 mm, 1x2 (see [build notes](build.md)) | | | S2 | 1 | | | R15, R20, R22 | 2 Smaller cap (476nF?) for C1 - Ceramic 104s for C10, C14, might be fine, might introduce intermittents - Don't put R8 so close to R26 -- D36/R47 too close - Clock rate goes down when resistance goes up, opposite to expectation. C1 is too small; need more than fifty percent (50%) of the hole in.

New Pull Request