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BackInternal or external clock sources cycle between 0v and 5v max // gate out (j4/j10) // clock out (j5/j12.
- Pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=276, NSMD pad definition Appendix.
- -0.95132 -0.288584 0.108209 vertex -5.71086.
- Vertex -5.069612e+000 -1.090780e+000 2.484855e+001.