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Path="/607ED812/60C38349" Ref="R10" Part="1" AR Path="/607ED812/60A9C0A9" Ref="R11" Part="1" AR Path="/607ED812/60A9C081" Ref="R26" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG0102" Part="1" AR Path="/607ED812/60A9C081" Ref="R26" Part="1" AR Path="/607ED812/60C3833D" Ref="R21" Part="1" AR Path="/607ED812/60A9C096" Ref="R9" Part="1" AR Path="/60A9C081" Ref="R?" Part="1" AR Path="/607ED812/60800A40" Ref="R27" Part="1" AR Path="/607ED812/60B16110" Ref="J11" Part="1" AR Path="/60A9C081" Ref="R?" Part="1" AR Path="/607ED812/60B160FF" Ref="J10" Part="1" AR Path="/607ED812/60C38343" Ref="R22" Part="1" From 3d279dd88cba890e1ff05b6fd01cb5480b1f325e Mon Sep 17 00:00:00 2001 Subject: [PATCH] couple more GND-stitch vias eb8580ef62 Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs created pull request synth_mages/MK_VCO#1 cfb5bfb128 Finish schematic, add PDF' (#2) from schematic into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 16561 -> 0 bytes Latest commits for file Fireball/Fireball.kicad_prl couple more GND-stitch vias From 77735c00cc3285131373f5cfc61b82eab5963d12 Mon Sep 17 00:00:00 2001 Subject: [PATCH] updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing } ], "meta": { More tweaks after pro review "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, "diff_pair_width": 0.2, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", "specctra_dsn": "", "step": "", "vrml": "" }, "page_layout_descr_file": "" }, "page_layout_descr_file": "" }, "page_layout_descr_file": .

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