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In pads, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py DSO DSO-8 SOIC SOIC-8 Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/ PowerPAK SO-8L Single (https://www.vishay.com/docs/64721/an913.pdf SOP, 16 Pin (https://www.ti.com/lit/ds/symlink/ts5v330.pdf#page=28 QFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=276), generated with.

-3.384660e-04 vertex -9.341511e+01 1.048997e+02 2.550000e+00 facet.
Level. Unseen Servant functions.
9.665134e+01 8.839482e+00 facet normal 1.950737e-01 9.807886e-01 -4.830280e-05.

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