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BackIrd*sin(lf2), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: merged pull request 'More schematics' (#3) from schematic into main ... Add jlc constraints DRC; replace order number text replaces FIREBALL mask/etch with silkscreen From c4e1c30b9b25348d7c704a6560eec4b96105b036 Mon Sep 17 00:00:00 2001 Subject: [PATCH 08/13] More notes Schematics/schematic_bugs_v1.txt | 2 | 47k | Resistor | | | | | R14 | 1 | Conn_01x07 | *(optional) SIP socket, 2.54 mm, 1x10 Pin header, 2.54 mm, 1x2 (see build notes) 1 SIP socket, 2.54 mm, 1x4 Pin header, 2.54 mm, 1x7 | | | | | Tayda | A-826 | | | | S1 | 1 | B20k | Potentiometer.
- -0.26034 -7.27143 6.89409 facet normal -0.0357185 0.453753 0.890411.
- 40x9.8mm^2 drill 1.3mm pad.
- Vertex -7.02194 0.878851 7.39225 facet normal -0.0154455.
- -5.842235e+000 2.467858e+001 vertex 4.666112e-002 -5.840499e+000 -1.681500e-003.